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Codasip opens up SDK for CHERI protection on RISC-V chips
Alliance commits to Integrating the architecture into all high-tech products
Software23 Oct 2024 | 1
CHERI
CHERI is an acronym for Capability Hardware Enhanced RISC Instructions, a research project from the University of Cambridge in the UK and US-based SRI International with the aim of adapting existing processor architectures to improve system security, at least as far as memory accesses go.
CHERI Alliance formed to promote memory security tech ... but where's Arm?
Updated Academic-industry project takes next step as key promoter chip designer licks its wounds
Research18 Jun 2024 | 3
FreeBSD Foundation hands out Beacon gongs for safer software
Multiple CHERI-related projects win money for important research that prizes safety over speed
Security26 Mar 2024 | 13
How Arm popped CHERI architecture into Morello Program hardware
Hot Chips Chip giant aims to adapt existing processor architectures to close off vulnerabilities in memory access
Systems26 Aug 2022 | 6
Biting the hand that feeds IT
